I often see the recommendation to sequence the placement of bypass caps in the order via - capacitor - pin. As this is not the way I do it, this part investigates the effect of not following this sequence.
I usually place a via as close as possible to the GND pin of the IC. If space permits, I place 2 vias at each PWR and GND pin. To see if there is a measureable difference when omitting the via closest to the GND pin I have drilled them away on the bottom side.
Then I have measured the GND bounce at the falling edge to see the difference.
The max value increased slightly from 89 mV to 101 mV. This is easily explainable by the increased inductivity of the GND connection.
The next question is whether VCC sag has also changed.
The voltage noise on-die has increased a little bit.
The primary goal of omitting the via is to create a filter with the additional track. The inductivity of this track should help to arrest the voltage noise on the IC side. So the last measurement is the voltage noise on the VCC plane of the PCB. But this voltage has increased, too. This is explainable due to the increased ESL of the decoupling caps. In the first case they were connected to the GND plane with 2 GND vias reducing their ESL value.
This experiment is for education only, as the function of the circuit is not impaired by the different via locations. It will work either way. But if I have a choice, I will put a via right on the pin.
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